Designing the Silicon Photonic physical layout for silicon photonic circuits, as well as for other domains like electronics, MEMS, and photonics, requires specialized software tools. These tools enable the creation of precise mask layouts necessary for fabricating circuits and components. There are a number of open-source options as well as commercial tools available for this purpose.
Open-source options include:
- KLayout: Primarily focused on polygon-based graphical editing, making it suitable for manually designing layout structures.
- Python and MATLAB: These environments allow for scripting-based layout generation through polygon-based scripts, providing flexibility for automated design.
- IPKISS: This tool also provides Python scripting and allows the creation of parameterized layouts for components and circuits, making it suitable for more automated layout generation.
In the commercial sector, a variety of tools are available for creating detailed layouts:
- Cadence Virtuoso Layout Suite
- Mentor Graphics Pyxis
- Synopsys IC Compiler
- Tanner LEdit
- LayoutEditor
- PhoeniX Software MaskEngineer
- WieWeb CleWin
- Design Workshop Technologies DW-2000
These tools cover the entire design workflow, including tasks such as schematic capture, physical layout creation, and verification processes like design rule checking (DRC), lithography simulation, and comparing the layout against the schematic. This comprehensive suite of tools is essential for silicon photonic circuit design to ensure that the design is manufacturable and meets the required specifications.
For example, Mentor Graphics Pyxis is highlighted as a core tool used for capturing schematics and performing physical layout in the design flow. Additionally, Eldo is used for electronic modeling and design, and together with other Mentor Graphics tools like Calibre, it facilitates design verification, physical layout optimization, and integration with manufacturing processes.
By using these tools in combination, designers can create intricate silicon photonic circuits that are ready for fabrication, ensuring that the layout meets design rules and is optimized for performance.